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CorePCIF v4.0
Table 4 · Device Speed Grade Requirements (Continued)
Performance Statistics
Family
Fusion
IGLOO/e
ProASIC3/E
ProASIC PLUS
RTAX-S (RTAX250S)
Commercial
–2
N/A
–2
N/A
N/A
Industrial
–2
N/A
–2
N/A
N/A
Military
N/A
N/A
–1
66 MHz 64-bit
RTAX-S (RTAX1000S to RTAX4000S)
Axcelerator (AX125 to AX500)
Axcelerator (AX1000 to AX2000)
RTSX-S
SX-A
SmartFusion2
IGLOO2
N/A
–1
–2
N/A
N/A
–1
–1
N/A
–1
–2
N/A
N/A
–1
–1
N/A
–1
–2
N/A
N/A
N/A
N/A
The PCI specification timing requirements are given in Table 5 .
Table 5 · PCI Bus Timing
Signals
Setup
Hold
Clock to Out
33 MHz
66 MHz
33 MHz
66 MHz
33 MHz
66 MHz
Bussed Signals
Non-Bussed Signals (e.g., GNTN)
7 ns
10 ns
3 ns
5 ns
0 ns
0 ns
0 ns
0 ns
11 ns
11 ns
6 ns
6 ns
Note: In SmartFusion2, timing closure at 66MHz is highly impacted by the other aspects of the design and resource
allocation. For highly congested designs it may not be possible in some cases to achieve a 66MHz solution. Priority
should be given to closing timing on the CorePCIF before moving onto other areas of the design.
v4.0
11
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